Design And Reuse

High-Speed SerDes Design: Architecture, Equalization, and CDR Circuits

High-Speed Serializer/Deserializer (SerDes) technology addresses these challenges by enabling efficient communication over ...
Design-Reuse

K-micro Introduces Second Generation Burst Mode CDR SerDes for GPON OLTs

Enables better FPGA-based OLT reference designs and multi-channel integration into ASICs for higher throughput and cost reduction SAN JOSE, Calif., March 23, 2009-- K-micro (Kawasaki Microelectronics ...
EDN

Specify an external reference clock to improve SERDES performance

The technical merits and economic benefits of high-speed serial data transmission on a circuit board or between neighboring circuit boards have led to the development of many high-speed serial ...
Electronic Design

CDR SerDes Cuts Power Consumption

Promising significant reductions in power and cost to passive-optical-network equipment makers, the MAX3886 multi-rate clock/data recovery (CDR) serializer/deserializer (SerDes) delivers data rates up ...
EDN

Multi-rate CDR chip integrates SerDes to reduce cost, save power

Sunnyvale, Calif.—Maxim Integrated Products has introduced the MAX3886 multi-rate, clock and data recovery (CDR) SerDes with data rates up to 2.488Gbit/s. By combining the functions of three ICs ...
Business Wire

eTopus Technology Announces Innovative SerDes Technology for Data Center, Cloud, Edge, and 5G Base Stations

The eTopus scalable, adaptive, low-power architecture for high-speed interconnects is in production and supported by technology leader SiFive SAN JOSE, Calif.--(BUSINESS WIRE)--eTopus Technology, a ...
Electronic Design

SERDES Chip Improves Signal Integrity, Provides For Real-Time Waveform Viewing

The VSC3441 high-speed serializer/deserializer (SERDES) from Vitesse Semiconductor incorporates clock and data recovery (CDR) circuits and advanced equalization to compensate for various impairments ...