The integration target is the Edu4Chip SoC platform. Both ASIC (GF 22 nm FDX) and FPGA prototyping targets are maintained. Create or pick a GitLab issue first. Create a branch for that issue. Open a ...
A systolic-array based AI accelerator for the Edu4Chip didactic SoC and includes RTL sources, Python golden models, cocotb testbenches, and Verilator-based simulation. This is a mirror repo from ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results