IEEE

A Novel High Speed 2-Step TDC-Based All-Digital DLL for DDR SDRAM Applications

Abstract: In sequential digital systems both Delay Locked Loops (DLLs) and the Phase Locked Loops (PLLs) are utilized for enhanced timings, i.e., to reduce the detrimental effects of distortion and ...
IEEE

Fast-Locking and High-Resolution DLL With Binary Search and Clock Failure Detection for Wide Frequency Ranges in 3-nm FinFET CMOS

Abstract: This article presents a digital delay-locked loop (DLL) with binary search (BS) locking, designed to cover a broad frequency-range from 533 MHz to 4.26 GHz. The BS locking scheme optimizes ...