Electronic Design

Tool Generates RTL Code From Untimed C++

The complexity of compute-intensive applications is driving the move to system design at the algorithmic level. With the release of the Catapult C synthesis tool, Mentor Graphics now offers the core ...
Semiconductor Engineering

Tool-Assisted LLM Targets RTL Code Generation (UC Riverside, Futurewei)

Researchers from University of California, Riverside and Futurewei published a technical paper titled “LLM4RTL: Tool-Assisted LLM for RTL Generation.” “Large language models (LLMs) have facilitated ...
Design-Reuse

ChipVision breakthrough ESL technology enables interactive creation of RTL code optimized for low-power consumption

Achieves up to 75 percent power savings in critical semiconductor blocks; significantly reduces development costs and design risk OLDENBURG, Germany and SAN JOSE, Calif. -- May 15, 2007 -- ChipVision ...
Design-Reuse

Real-World Reuse: RTL Recycling

In the real world of electronic product design, time-to-market can have a large impact on success. To facilitate production speed, RTL from existing projects is often recycled for use in the new ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...
Semiconductor Engineering

Choosing The Right Superlinting Technology For Early RTL Code Signoff

No one can afford to go through weeks of verification only to discover problems in the register- transfer level (RTL) code that might not be functionally wrong, but do not follow established rules for ...
EDN

Give the people what they want: HLS for RTL verification

As the manual RTL design flow stumbles under the burden of titanic designs, an excessive burden is placed on RTL verification teams to meet expectations for design cycle time and quality of results ...