EDN

Physical RTL optimization solves problems early

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...
EDN

RTL coding architecture affects power estimation & analysis

A well thought out design flow for SoCs ensures that the resulting device meets the requirement of low power dissipation. To meet these goals at the device level, individual modules (or components of ...
Semiconductor Engineering

Top Five Trends In RTL Signoff

The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...
Design-Reuse

Adaptive Silicon and Atrenta Partner to Provide RTL Coding Rules for Programmable Logic Cores

LOS GATOS, Calif./SAN JOSE, Calif. - October 8, 2001 - Adaptive Silicon, Inc. (ASi) of Los Gatos, Calif., and Atrenta Inc. of San Jose, Calif., today announced that ASi is developing an Adaptive ...
Semiconductor Engineering

Choosing The Right Superlinting Technology For Early RTL Code Signoff

No one can afford to go through weeks of verification only to discover problems in the register- transfer level (RTL) code that might not be functionally wrong, but do not follow established rules for ...